1,008 Verification Engineer jobs in the Philippines

We are adding a Digital Verification Engineer skilled in Verification and Debug of high-speed I/O Circuits.

Responsibilities may include, but are not limited to
:

• Verification plan for high speed sub-systems including ethernet, DDR.
• Define coverage goals with corner cases and metrics aligning with standards
• Understand microarchitecture to ID verification critical paths
• Perform functional and timing simulations using EDA tools (Synopsis VCS, Cadence Xcellium, Questa)
• Build and Develop reusable UVM testbenches for block and chip level Verification
• Validate timing closure and signal integrity across high-speed interfaces
• Collaborate with designers to simulate digital and AMS blocks
• Drive code coverage closure
• Debug failing test cases using waveform viewers, assertion logs, and transaction level traces
• Establish and maintain regression to ensure continuous verification of evolving
  RTL
• Interact with cross functional teams to align DV Goals. Participate in design reviews and ensure system level requirements
• Support pre-silicon bring up and debug of silicon prototypes.

Qualifications – Minimum Requirements
:

• 7+ years Digital Design Verification
  experience of complex high speed IO sockets
• Proficiency in System Verilog and
  UVM
  for
  testbench development and functional verification
• EDA tool experience
  (Synopsis VCS, Cadence Xcelium, Siemens Questa and Waveform viewers (Simvision, Verdi)
• Protocol Verificaiton of High-Speed I/O Circuits (ethernet, DDR)
• Solid understanding of timing analysis, signal integrity and mixed signal simulations
• Scripting languages (Python, PERL, TCL)
• Execute coverage driven verification plans
• Debuggin Complex RTL issues
• Formal Verification and assertion based techniques.

Job Summary:

The Staff Design Verification (DV) Engineer is responsible for setting the verification policies, managing verification activities, preparing verification packages for clients and maintaining verification assets.

As a staff engineer, the role can also include involvement in research and development, process development, process improvement, resource planning, team development, project leading, and client communication.

Key Responsibilities:

● Establish and improve systems and processes related to design verification

● Provide leadership to design verification projects

● Verify digital designs up to system-level

● May verify analog-mixed signal blocks that interface to digital blocks

● Identify test cases and develop verification plans based on design specifications

● Develop testbenches and testbench components such as models, monitors and scoreboards

● Perform test implementation, simulation and debugging

● Design regression testing environments

● Perform regression testing, coverage collection and analysis

● Prepare verification packages for clients

● Project management

● Coach junior design verification engineers

● Collaborate with design team and other stakeholders to deliver on-time and high-quality design verification

● Review output of junior members of the team to ensure quality of design verification

● Develop and promote best practices for design verification

● Manage verification assets

● Provide support to customers

Key Qualifications:

• BS or MS in Electrical Engineering, Electronics Engineering, Computer Engineering or related courses
• With at least 10 years of digital or analog-mixed signal design verification work experience

Design Verification Process & Technology Domain:

• Expert in all phases of design verification - verification plan creation, testbench creation, test suite implementation, simulation & debugging, coverage collection & analysis, and regression testing
• Experience in analog-mixed signal verification is preferred
• Proficient in industry standard protocols such as AXI, AHB, PCIe, and I2C
• Expert in multiple technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)

EDA Tools:

• Expert in using simulation tools such as VCS, Incisive/Xcelium, and Questa

Language & Methodology:

• Expert in HVL and methodologies (Verilog, SystemVerilog, UVM)
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Nice to have:

• Ability to standardize and improve development processes
• Excellent communication and presentation skills, both written and spoken English
• Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
• Ability to work in a team operating across multiple sites
• Ability to plan and organize project activities
• Ability to lead a design verification team
• Ability to coach junior engineers

Job Type: Full-time

Benefits:

• Company events
• Flextime
• Health insurance
• Opportunities for promotion
• Promotion to permanent employee

Experience:

• UVM: 3 years (Required)
• Design Verification: 5 years (Preferred)
• TCL: 3 years (Preferred)

Work Location: In person

Job Summary:

We are looking for an experienced 
Senior Design Verification Engineer
 to take ownership of design verification projects, from block-level to system-level, ensuring high-quality, reliable designs. This role combines technical expertise with leadership responsibilities, providing an exciting opportunity to mentor junior engineers and collaborate on innovative projects.

Key Responsibilities:

• Verifying digital designs at all levels and supporting analog-mixed signal interfaces.
• Developing verification plans and create test benches, models, and test cases.
• Executing simulation, debugging, regression testing, and coverage analysis.
• Leading design verification projects, ensuring quality and timely delivery.
• Mentoring junior engineers and reviewing their work to maintain standards.
• Collaborating with cross-functional teams and driving best practices in verification.

Qualifications

• Education:
   BS in Electrical, Electronics, or Computer Engineering, or related fields.
  Master's/PhD is a plus
• Experience:
   8 to 10+ years in digital or analog-mixed signal design verification.
• Technical Skills:
• Proficient in design verification processes, including simulation tools (VCS, Incisive/Xcelium, Questa).
• Proficient in one or more technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)
• Knowledge of protocols like AXI, AHB, PCIe, and I2C.
• Expertise in HVL (Verilog, SystemVerilog, UVM) and scripting (Perl, Tcl).
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Accountabilities
Responsibilities & Skills

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
• Understand the specifications, use cases and develop System Verilog and 'C' based testbenches in UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
• Define and design verification regression environment
• Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
• Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
• Develop best practices and world class methods for SoC verification

Required Skills

• 6-10 years Digital Design Verification Related Experience
• Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
• Skill in debugging and analyzing complex digital design
• Experience in HDL and HVL Languages and Methodologies
• Experience in ASIC/FPGA/SoC verification or development cycle
• Experience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
• Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
• Strong communication, analytical and documentation skills and ability to interface with other groups/site
• Stay up to date on industry trends and direction of verification technology development

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

Job Summary:

The Staff Design Verification (DV) Engineer is responsible for setting the verification policies, managing verification activities, preparing verification packages for clients and maintaining verification assets.

As a staff engineer, the role can also include involvement in research and development, process development, process improvement, resource planning, team development, project leading, and client communication.

Key Responsibilities:

●   Establish and improve systems and processes related to design verification

●   Provide leadership to design verification projects

●   Verify digital designs up to system-level

●   May verify analog-mixed signal blocks that interface to digital blocks

●   Identify test cases and develop verification plans based on design specifications

●   Develop testbenches and testbench components such as models, monitors and scoreboards

●   Perform test implementation, simulation and debugging

●   Design regression testing environments

●   Perform regression testing, coverage collection and analysis

●   Prepare verification packages for clients

●   
Project management

●   Coach junior design verification engineers

●   Collaborate with design team and other stakeholders to deliver on-time and high-quality design verification

●   Review output of junior members of the team to ensure quality of design verification

●   Develop and promote best practices for design verification

●   Manage verification assets

●   Provide support to customers

Key Qualifications:

• BS or MS in Electrical Engineering, Electronics Engineering, Computer Engineering or related courses
• With at least 10 years of digital or analog-mixed signal design verification work experience

Design Verification Process & Technology Domain:

• Expert in all phases of design verification - verification plan creation, testbench creation, test suite implementation, simulation & debugging, coverage collection & analysis, and regression testing
• Experience in analog-mixed signal verification is preferred
• Proficient in industry standard protocols such as AXI, AHB, PCIe, and I2C
• Expert in multiple technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)

EDA Tools:

• Expert in using simulation tools such as VCS, Incisive/Xcelium, and Questa

Language & Methodology:

• Expert in HVL and methodologies (Verilog, SystemVerilog, UVM)
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Nice to have:

• Ability to standardize and improve development processes
• Excellent communication and presentation skills, both written and spoken English
• Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
• Ability to work in a team operating across multiple sites
• Ability to plan and organize project activities
• Ability to lead a design verification team
• Ability to coach junior engineers

Position

・ Senior Engineer

Experience and knowledge

・Large scale RTL design over 100k gate in Verilog HDL and VHDL, including architecture investigation, logic design, logic verification, timing optimization for the critical path

・Extracting the verification items from the specification

・Creating the testbench and verifying on the bench

Educational background

・ Bachelor's degree in computer engineering, electronics, electronics and communications engineering, computer science or similar course

Language

・ English

・ Japanese (not required)

Working days and hours

Mon to Fri, 8am to 5pm

Work location

・ Philippines

・ Germany

・ Japan

Description
Power Integrations
designs and manufactures high-performance electronic components which are used in a range of power-conversion systems. Our integrated circuits enable compact, energy-efficient AC-DC power supplies for a vast range of electronic products including mobile devices, TVs, PCs, appliances, smart utility meters and LED lighting. Our SCALE IGBT drivers enhance the efficiency, reliability and cost of very high-power applications such as industrial motor drives, solar and wind energy systems, electric vehicles, and high-voltage DC transmission.

Job Summary
As a Staff Mixed-Signal IC Design and Verification Engineer, your primary role involves design and verifying of Mixed Mode Integrated Circuits that combine both, analog and digital components. Responsibilities include developing verification strategies, creating testbenches, and designing test cases for mixed-signal functionality. You'll collaborate closely with analog and digital design teams, use simulation tools to ensure accurate performance, and debug issues. Strong expertise in mixed-signal verification methodologies, understanding of analog and digital circuitry, and proficiency in simulation tools are crucial for success in this role

Key Responsibilities

• Work closely with cross-functional teams, including digital design, analog design, and test.
• Develop verification plans for testing mixed-signal IC functionality.
• Design and implement testbenches to verify analog and digital components of mixed-signal circuits.
• Conduct simulations to ensure correct functionality and performance of mixed-signal circuits under various conditions.
• Analyze simulation results, identify issues, and collaborate with design teams to resolve problems in the IC.
• Create and maintain documentation for verification processes, methodologies, and results.
• Utilize relevant EDA tools for simulation and verification tasks.
• Collaborate with test engineering teams to transition from simulation to actual hardware testing.
• Provide guidance and mentoring to junior engineers and contribute to improving verification processes.

Requirements

• BS degree in Electronics Engineering or related course .
• 8 years of experience working in an IC design and verification environment.
• Have worked on verifying designs which have gone into production.
• Have a solid understanding of electronics principles and basic functions (Comparators, OpAmps, DACs, ADCs, Bandgaps, etc.)
• Have a strong understanding of mixed signal verification principles and current methods.
• Expert in both analog and digital simulation tools (preferably Cadence based)
• Familiar with languages such as Verilog, SystemVerilog or VerilogAMS.
• Have experience in using behavioral models as part of the verification flow.
• Have working knowledge of MS Word, Excel and PowerPoint.
• Have excellent verbal, written and presentation communication skills.
• Comfortable working in a process driven, ISO 9000 framework for new product introduction.
• Produce accurate documentation to the highest standards of completeness and precision for presentation.

Job Qualifications:

• Must be a graduate of Bachelor of Science in Industrial Engineering.
• Computer Literate.
• Knowledgeable on 7 QC core tools is an advantage.

Job Responsibilities:

• Conduct analysis together with concerned SVs and other personnel to determine the root cause of the problem, recommends and verifies implementation and effectiveness of countermeasure.
• Review adequacy and compliance to Procedure.
• Conducts internal & supplier audits.
• Prepares PPAP documents.
• Participate in quality optimization.

ensures a project's products or services meet specific quality standards by overseeing processes, managing documentation, conducting inspections, and resolving issues to prevent defects and guarantee client satisfaction