484 Design Verification jobs in the Philippines

We are adding a Digital Verification Engineer skilled in Verification and Debug of high-speed I/O Circuits.

Responsibilities may include, but are not limited to
:

• Verification plan for high speed sub-systems including ethernet, DDR.
• Define coverage goals with corner cases and metrics aligning with standards
• Understand microarchitecture to ID verification critical paths
• Perform functional and timing simulations using EDA tools (Synopsis VCS, Cadence Xcellium, Questa)
• Build and Develop reusable UVM testbenches for block and chip level Verification
• Validate timing closure and signal integrity across high-speed interfaces
• Collaborate with designers to simulate digital and AMS blocks
• Drive code coverage closure
• Debug failing test cases using waveform viewers, assertion logs, and transaction level traces
• Establish and maintain regression to ensure continuous verification of evolving
  RTL
• Interact with cross functional teams to align DV Goals. Participate in design reviews and ensure system level requirements
• Support pre-silicon bring up and debug of silicon prototypes.

Qualifications – Minimum Requirements
:

• 7+ years Digital Design Verification
  experience of complex high speed IO sockets
• Proficiency in System Verilog and
  UVM
  for
  testbench development and functional verification
• EDA tool experience
  (Synopsis VCS, Cadence Xcelium, Siemens Questa and Waveform viewers (Simvision, Verdi)
• Protocol Verificaiton of High-Speed I/O Circuits (ethernet, DDR)
• Solid understanding of timing analysis, signal integrity and mixed signal simulations
• Scripting languages (Python, PERL, TCL)
• Execute coverage driven verification plans
• Debuggin Complex RTL issues
• Formal Verification and assertion based techniques.

Job Summary:

The Staff Design Verification (DV) Engineer is responsible for setting the verification policies, managing verification activities, preparing verification packages for clients and maintaining verification assets.

As a staff engineer, the role can also include involvement in research and development, process development, process improvement, resource planning, team development, project leading, and client communication.

Key Responsibilities:

● Establish and improve systems and processes related to design verification

● Provide leadership to design verification projects

● Verify digital designs up to system-level

● May verify analog-mixed signal blocks that interface to digital blocks

● Identify test cases and develop verification plans based on design specifications

● Develop testbenches and testbench components such as models, monitors and scoreboards

● Perform test implementation, simulation and debugging

● Design regression testing environments

● Perform regression testing, coverage collection and analysis

● Prepare verification packages for clients

● Project management

● Coach junior design verification engineers

● Collaborate with design team and other stakeholders to deliver on-time and high-quality design verification

● Review output of junior members of the team to ensure quality of design verification

● Develop and promote best practices for design verification

● Manage verification assets

● Provide support to customers

Key Qualifications:

• BS or MS in Electrical Engineering, Electronics Engineering, Computer Engineering or related courses
• With at least 10 years of digital or analog-mixed signal design verification work experience

Design Verification Process & Technology Domain:

• Expert in all phases of design verification - verification plan creation, testbench creation, test suite implementation, simulation & debugging, coverage collection & analysis, and regression testing
• Experience in analog-mixed signal verification is preferred
• Proficient in industry standard protocols such as AXI, AHB, PCIe, and I2C
• Expert in multiple technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)

EDA Tools:

• Expert in using simulation tools such as VCS, Incisive/Xcelium, and Questa

Language & Methodology:

• Expert in HVL and methodologies (Verilog, SystemVerilog, UVM)
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Nice to have:

• Ability to standardize and improve development processes
• Excellent communication and presentation skills, both written and spoken English
• Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
• Ability to work in a team operating across multiple sites
• Ability to plan and organize project activities
• Ability to lead a design verification team
• Ability to coach junior engineers

Job Type: Full-time

Benefits:

• Company events
• Flextime
• Health insurance
• Opportunities for promotion
• Promotion to permanent employee

Experience:

• UVM: 3 years (Required)
• Design Verification: 5 years (Preferred)
• TCL: 3 years (Preferred)

Work Location: In person

Job Summary:

We are looking for an experienced 
Senior Design Verification Engineer
 to take ownership of design verification projects, from block-level to system-level, ensuring high-quality, reliable designs. This role combines technical expertise with leadership responsibilities, providing an exciting opportunity to mentor junior engineers and collaborate on innovative projects.

Key Responsibilities:

• Verifying digital designs at all levels and supporting analog-mixed signal interfaces.
• Developing verification plans and create test benches, models, and test cases.
• Executing simulation, debugging, regression testing, and coverage analysis.
• Leading design verification projects, ensuring quality and timely delivery.
• Mentoring junior engineers and reviewing their work to maintain standards.
• Collaborating with cross-functional teams and driving best practices in verification.

Qualifications

• Education:
   BS in Electrical, Electronics, or Computer Engineering, or related fields.
  Master's/PhD is a plus
• Experience:
   8 to 10+ years in digital or analog-mixed signal design verification.
• Technical Skills:
• Proficient in design verification processes, including simulation tools (VCS, Incisive/Xcelium, Questa).
• Proficient in one or more technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)
• Knowledge of protocols like AXI, AHB, PCIe, and I2C.
• Expertise in HVL (Verilog, SystemVerilog, UVM) and scripting (Perl, Tcl).
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Accountabilities
Responsibilities & Skills

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project
• Verify design blocks, sub systems and full chip using assertion-based verification, formal verification, directed tests and randomized tests
• Understand the specifications, use cases and develop System Verilog and 'C' based testbenches in UVM environment
• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
• Define and design verification regression environment
• Perform Functional coverage, RTL code coverage, assertion coverage, and gate level simulations
• Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on aggressive time schedules
• Develop best practices and world class methods for SoC verification

Required Skills

• 6-10 years Digital Design Verification Related Experience
• Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer
• Skill in debugging and analyzing complex digital design
• Experience in HDL and HVL Languages and Methodologies
• Experience in ASIC/FPGA/SoC verification or development cycle
• Experience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa
• Hands-on experience in Python, Perl or Shell Scripting, TCL and Make.
• Strong communication, analytical and documentation skills and ability to interface with other groups/site
• Stay up to date on industry trends and direction of verification technology development

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

Job Summary:

The Staff Design Verification (DV) Engineer is responsible for setting the verification policies, managing verification activities, preparing verification packages for clients and maintaining verification assets.

As a staff engineer, the role can also include involvement in research and development, process development, process improvement, resource planning, team development, project leading, and client communication.

Key Responsibilities:

●   Establish and improve systems and processes related to design verification

●   Provide leadership to design verification projects

●   Verify digital designs up to system-level

●   May verify analog-mixed signal blocks that interface to digital blocks

●   Identify test cases and develop verification plans based on design specifications

●   Develop testbenches and testbench components such as models, monitors and scoreboards

●   Perform test implementation, simulation and debugging

●   Design regression testing environments

●   Perform regression testing, coverage collection and analysis

●   Prepare verification packages for clients

●   
Project management

●   Coach junior design verification engineers

●   Collaborate with design team and other stakeholders to deliver on-time and high-quality design verification

●   Review output of junior members of the team to ensure quality of design verification

●   Develop and promote best practices for design verification

●   Manage verification assets

●   Provide support to customers

Key Qualifications:

• BS or MS in Electrical Engineering, Electronics Engineering, Computer Engineering or related courses
• With at least 10 years of digital or analog-mixed signal design verification work experience

Design Verification Process & Technology Domain:

• Expert in all phases of design verification - verification plan creation, testbench creation, test suite implementation, simulation & debugging, coverage collection & analysis, and regression testing
• Experience in analog-mixed signal verification is preferred
• Proficient in industry standard protocols such as AXI, AHB, PCIe, and I2C
• Expert in multiple technology domains such as sensors, video & image processing, security and SoC infrastructure (memory, I/O, bus controllers)

EDA Tools:

• Expert in using simulation tools such as VCS, Incisive/Xcelium, and Questa

Language & Methodology:

• Expert in HVL and methodologies (Verilog, SystemVerilog, UVM)
• Proficient in C/C++ or other high-level programming language
• Proficient in scripting such as Perl, shell scripting and Tcl

Nice to have:

• Ability to standardize and improve development processes
• Excellent communication and presentation skills, both written and spoken English
• Aggressive in learning, strong problem solving, decision-making and troubleshooting skills
• Ability to work in a team operating across multiple sites
• Ability to plan and organize project activities
• Ability to lead a design verification team
• Ability to coach junior engineers

Position

・ Senior Engineer

Experience and knowledge

・Large scale RTL design over 100k gate in Verilog HDL and VHDL, including architecture investigation, logic design, logic verification, timing optimization for the critical path

・Extracting the verification items from the specification

・Creating the testbench and verifying on the bench

Educational background

・ Bachelor's degree in computer engineering, electronics, electronics and communications engineering, computer science or similar course

Language

・ English

・ Japanese (not required)

Working days and hours

Mon to Fri, 8am to 5pm

Work location

・ Philippines

・ Germany

・ Japan

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on LinkedIn and Twitter (X).

The Group
The charter of ADI's CSS team is to lead the market in selected technology domains with highly differentiated sensing and signal processing solutions. Today these technology areas include Capacitive Sensing, Optical Image Stabilization and Audio that drive growth in our portable and non-portable consumer business.

As part of our global operation and expanding business needs, we are now seeking to fill key roles in defining, developing, and verifying digital systems for this key market area. This would scan the entire development cycle from concept phase, through design, verification, implementation, and release of products to customers.

Responsibilities
This position will be responsible for contributing to:

• Verification of complex designs and sub-systems using leading edge verification methodologies
• Contribute and influence the decisions on methodologies to be adopted for the verification.
• Technically mentor and guide junior verification engineers on SoC Verification.
• Architect the testbench and develop in UVM or Formal based verification approaches. Integrate the block testbench in chip-level UVM environment and verify integration.
• Define test plans, tests, and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
• Continuous interaction with analog co-sim and firmware team in enabling top-level chip verification aspects.
• Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team

Qualifications

• Bachelor's or master's degree, in Engineering (Electronic Engineering) or equivalent
• 5+ years ASIC design, verification, or related work experience.

Additional Preferred Qualifications

• Proficient in developing unit and SoC level test benches using VMM/OVM/UVM
• Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
• Experience working with Cortex-M series-based processors
• Experience in Gate Level Simulation (GLS) verification flow for SoC verification.
• Experience of pre and post-silicon verification test flow and automated test benches
• Verilog, C/C++, System C, Java, TCL/Perl/Python/shell-scripting
• Building and leading verification teams is a plus
• RTL design/front-end design/FPGA flow (Intel Cyclone VE / Xilinx ZCU104) experience
• Formal verification methodology
• Strong interpersonal, teamwork and communication skills are required.
• Be self-motivated and enthusiastic

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: Normal Time (Philippines)

Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the brightest minds to collaborate on solving complex problems that matter from autonomous vehicles, drones and factories to augmented reality and remote healthcare.

ADI fosters a culture that focuses on employees through beneficial programs, aligned goals, continuous learning opportunities, and practices that create a more sustainable future.

About Analog Devices

Analog Devices, Inc. (NASDAQ:

ADI

) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at

and on

LinkedIn

and

Twitter (X)

.

Design Verification Engineer

About the Role

As a Design Verification Engineer at Analog Devices, you will develop test benches and perform design verification of new digital, analog, and mixed-signal products prior to tape-out. You'll create advanced environments that support comprehensive, metric-driven verification processes and ensure the accuracy and reliability of designs through code coverage analysis. Working with moderate supervision, you'll collaborate with cross-functional teams to meet project timelines and quality standards, applying your technical expertise to solve verification challenges.

Key Responsibilities

• Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies
• Create and maintain verification plans, focusing on functional and code coverage metrics to ensure design quality
• Perform black box testing for complex designs to identify potential issues early in the verification cycle
• Debug verification issues using advanced troubleshooting techniques and provide effective solutions
• Collaborate with design teams to align verification strategies with project requirements
• Create and maintain detailed documentation for verification processes and results
• Participate in design reviews and provide verification insights to improve overall product quality
• Apply scripting skills to automate verification tasks and improve efficiency

Must Have Skills

• SystemVerilog and UVM: Proficiency in developing and maintaining verification environments using SystemVerilog and Universal Verification Methodology for complex designs
• Test Bench Development: Ability to develop comprehensive test benches for mixed-signal product verification, focusing on coverage-driven methodologies
• Scripting: Capability to create and implement automation scripts using Python, Perl, or TCL to enhance verification workflows
• Verilog RTL: Strong understanding of Register Transfer Level design concepts and their application in verification
• EDA Tools: Experience with electronic design automation tools and simulators for effective design verification
• Debugging: Demonstrated ability to analyze and resolve moderately complex verification issues with limited supervision
• Communication Protocols: Working knowledge of standard interfaces such as I2C, SPI, and UART, and their verification requirements

Preferred Education and Experience

• Bachelor's or Master's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field
• 2-4 years of relevant experience in digital design verification

Why You'll Love Working HereAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.

You'll have access to continuous learning opportunities and mentorship from industry experts. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Graduate Job

Required Travel: No

Join Silicon Verified Consultancy Inc.

QUALIFICATIONS Experienced Design Verification Engineer

• 5 to 10 years working experience in Front-End Design Verification with proven ability to actively contribute to IP-level digital logic design, implementation, and verification projects from a chip/sub-system/sub-block level using:

• SystemVerilog in a UVM environment;

• ASIC/FPGA/SOC design flow/development cycle;
• EDA simulation tools like Synopsys VCS, Mentor Questa, or Cadence IES/XCELIUM
• Robust debugging and problem-solving skills supported by relevant bug reporting/fixing experience.

• Having the following skills would be an advantage:

• RTL Design/Digital Implementation

• Chip-level FW co-verification using C tests in UVM environment
• Formal Property Verification
• Automation using Shell Scripting, Make, Python or Perl

• Familiarity with or Experience in two or more of the following:

• NVMe, PCIe, or Advanced Microcontroller Bus Architecture (AMBA) standards;

• Functional Verification and/or RTL design of Memory Controller, Error Detection & Correction, Error Correction Codes (ECC), Security & Cryptography blocks.
• Excellent written and verbal communication skills.
• Having an active nonimmigrant US visa or Canada visa/eTA is a plus.